Superconductive associative memory system



July 20, 1965 P. M. DAVI ES SUPERCONDUCTIV ASSOCIATIVE MEMORY SYSTEMFiled May 15, 1961 S Sheets-Sheet 1 FI/Z6. 5.

July 20, 1965 P. M. DAvlEs SUPERCONDUCTIVE ASSOCIATIVE MEMORY SYSTEM 3Sheets-Sheet 2 Filed May 15, 1961 PAK/L IW. a4 V/E'S INVENTOR.

July 20, 1965 P. M. DAvn-:s 3,196,407

SUPERCONDUCTIV ASSOCIATIV MEMORY SYSTEM I Filed May 15, 1961 3Sheets-Sheet 3 United States Patent O This invention relates to a memorystorage system and more particularly to a self searching memory in whichinformation may be stored and retrieved without the need of specifyingan address.

The basic system was iirst disclosed in co-pending application SerialNo. 76,368, entitled Self Searching Memory, lby Paul M. Davies, `andassigned to the same common assignee. The present disclosure representsan improvement in simplifying the structure and extending thecapabilities of the system. In particular, the memory ycells have beenchanged to improve certain time constants and a new memory module isused in place of both the original key and the data modules. This newmemory module is capable of being used either as a data or key module.The time constant associated with reading is improved by selecting arecord in the absence of resistance in a series network rather than bydetecting the presence of resistance in a plurality of networksconnected in parallel. Details of the new memory module are more fullydescribed and claimed in co-pending application Serial No. 109,924,entitled Memory Modules for a Self Searching Memory and assigned to thesame common assignee. The advantages of the present system over theprior art will now be described.

In some prior art memory systems memory Icells are Vassigned consecutivenumbers which serve as addresses. In order to write a record into such amemory the address of an empty cell must first be specified. rhe systemdecodes this address, which is used to obtain access to the speciiicmemory cell corresponding to the specified address. In magnetic tapememory systems a count-up or countdown addressing system is used inwhich the tape is read and the cells counted until the speciiied cell isreached. Lin core memory systems the specified address controlsswitching matrices which select the proper memory cell. In all the priorart systems the address of an empty cell must be known beforehand or, inlieu of this, a sequential Search must be made in order to find an emptycell which must then be suitably identified.

In order t-o retrieve information already stored in conventional memorysystems it is necessary to either specify the address, which must thenbe decoded, or a search must be made to find the desired memory cell onthe basis of information contained in the record itself. ln manyapplications such a search would require on the average half as manyread operations as there are cells in the memory, thereby making such anoperation prohibitively expensive and time consuming.

ln this invention, as presumably in the case of the human brain,information is stored in a memory cell without specifying a particularmemory address. It is ree quired only that at least one memory cell beempty for the information to be recorded. Further, it is not necessaryto know which memory cells are full and which memory cells are empty,provided only that a memory cell is available to receive the informationto be stored. Reading of information is achieved by specifying keyinformation which is carried as part of the stored record and whichuniquely defines the stored record. When this keyinformation isspecified, a simultaneous search is made in all memory cells, and thestored record with the matching key information is automaticallyread-out, there being no requirement to know exactly in which memory3,196,497 Patented July 20, 1965 cell the information was stored.Details of the circuitry for selecting the deiined first memory cell aremore fully described and claimed in co-pending application Serial No.76,182, now abandoned, entitled Memory Cell Selecting Means.

in the performance of this invention it will be pointed out howcryogenic devices are particularly suited for performing the functionsof the self searching memory device due to the infinite ratio of ONresistance (resistive state) to .OFF resistance (superconductive state)thereby permitting complex networks with no attenuation of signal.

Further objects and advantages will be made more apparent as thedescription progresses, reference now being made to the accompanyingdrawings wherein:

FIG. l is a block diagram of a memory storage device;

FIG. 2 is a schematic diagram of a switching network suitable forselecting the lirst available memory cell;

FIG. 3 is a schematic diagram of a control module illustrated in FIG. l;

4IG. 4 is a schematic diagram of an individual bit handling segment anumber of which comprise the memory module illustrated in FIGS. l and 3;

FIG. 5 is a cross sectional view of a dual control gate elementillustrated in FIG. 4; and

FIG. 6 is a schematic diagram of a memory storage device illustrated inFIG. l and utilizing the control modules of FIG. 3 and the memorymodules comprised of memory segments illustrated in FIG. 4.

in order to explain more fully the advantages to be obtained from thepresent invention, it is though best at this time to elaborate on thedesired functional coopera tion of the elements comprising the discloseddevice and leave for a latter part of the speciiication the actualdisclosure and operation of the individual components.

Referring now to FIG. l, there is shown a memory block comprising aplurality of individual memory cells each having the capacity to store acomplete record. Each memory cell is divided into two parts identifiedas a control module and a memory module in contradistinction with theaforementioned co-pending patent applications that require :three partsfor each memory cell. Cooperating with the memory block is a single Mregister for communicating with the individual modules of the memorycells. The vertical lines from the individual modules of the M registerinterconnect all the'memory cells of :the memory block and are used totransfer a record to and from the M register and the memory cells of thememory block.

The operation of the memory device will be more apparent by consideringa writing operation in which information is caused to transfer from theM register to a memory cell in the memory block. To writel information,it is necessary to place a record Iin the memory module of the Mregister and transfer this record to the memory module of the first-selected memory cell. The control module of the M register is caused togenerate control pulses which are directed via the vertical linesassociated with all of the individual control modules of all the memorycells, to each control module. Each control module of each memory cellcontains a busy flip-liep circuit which indicates whether or not thatparticular memory cell contains a record. The control pulses generatedby the control module of the M register, interrogato all busy hip-ilops,and by means of logic circuits in every control module, rthe first emptymemory cell as measured from the M register is selected. Having locatedthe first empty memory cell, .the record in the M register istransferred into the selected memory cell along the vertical linesinterconnecting all memory modules. Once the memory cell is loaded withrecord information, the busy flin-flnn compared signal. H l l Y controlmodule'generates a read signal which is directed of Yth'atmemory cell isturned ON to indicate the memory cell i's full and hence'ot available.t'

Inrorder to read a Ispecified record contained 1n a full memory cell, itis necessary toload into the memory module of the-Mregister, byinformation that uniquelyJ identies the desired record. n i Y registergenerates a read command signal which, together with thekey vinformationlocatedin the" key module of the M register, is sent to all memory cellsinthe memory block. The key information'is transmitted along theselected vertical line-s to all' memory modules of the memoryblock andis simultaneously compared with the information lstored in similarportions of all memory modulesthrough'which the'vertical lines pass.Each b ithandling segment compares the stored information with thetransmitted information and when the same, a superconducting device-remains'superconductive, whereas lif they differ, `:the device becomesresistive.l Since each bit handling lsegmentV has such a'device :and allof saidV devices in any, given memory module are connected in series, itis only necessaryto detect the seriesr path without resistance to selectthe desired-memory cell. Since the key information i'sfunique, only onememory cell will Yhave a true compared signal while all others will havea false Once the memory cellis selected the to those individual bithandling ksegments of the memory module not lused for key informationfor reading the s-tored'information into -theM register. It can be seen,therefore, that all memory cells'areginterrogated simultaneously andthatthe logic cicruits associated with the memory cells themselvesandlin'cooperation with thev M register will cause information tomberead-out to that viously used for key information. I V

A important feature-of each memory cell is the ability to clear an'individual memory cell by simply turning VFFthe busy hip-flop in thecontrol module. In` operation,`cle'a"ring is Vaccom'plishefcl by placingthe key informaton'- corresponding to`V the"'particula'r'data to becleared in th'e` M' register. A vclearcoiitrolcommand signal is gen'- itir contr-ormonale finie M register, andiin a mannersmilaij'fto'that'v-described for the readoperation,

tleindividnal-k'ey modules are inte''rrogatedl V'The truev lcorparedsignal' 'ge nien Icooperfates wi n A intheseleotedicontol module to turnoff the Ibusyflipnerat'ed/in the selectedfkey module "the clear controlcommand signal -irg`lstred` for-'a motor vehicle registry office yusingcards.A Theindividual records maybe yuniquely defined in terms oflicensev'plate number, enginexnumben body lllll'lb' number ypreferrdheadig however,- ech 'heading wouldrequire veither'duplicate'jcardsor 'crossiilin'g vitechriiques to locate the'actual'infoirriationvcafd- In'thepresentlinyention any information thaturii`c'1t1ely-'l defines fthe 'vehicle A'or owner name"ar'id"addressrvofowne'r' oi socialV security Obvou'sl'ya card index may be setl up forany ingjthe "recordwill be `'r'efcor'ded the memory moduleand'anypor'tion-ofthe Vrecord can beu'sed lasrthe key.

Thesuitfability vo'fafilizin'g cryogenic devices in the' self :searchingmemory will now- 'be desc'zr'ibed by considering' thenature oftheindividual 'componentsand the functions they must-perform.`Theessenti'al idea of the self searching memory is the use of logic ineach memory cell to rnake'grthe;specific selection; whetherit be forreading,

writing,A or clearing. This logic must be performed sifmultaneouslyrinall cells ofthe memory if the1desiredincreaseA-inms/earching speed 'is to be realized. Ofnecescircuitrymust'be complicated, .since in the writ-V mg operationv it `is necessaryVto form a decis-ion at each `r'renory cell that'is a function of thebusy flip-flops of. all

previous 'cells,4 in order to select the first empty cell.

portion of the memory module'lof the MYA register not prev Thecontrol'module of the M Y The adaptability of cryogenic devices to thismemory systern is due mainly to the abil-ity of a gate elementV to beswitched from a superconductive state to a resistive state by theappilcation of a suitable current in a control element held in fluxlinking relationship with said gate element. Y

Superconductvity as used -in the present invention is the` apparentdisappearance of electrical resistance at Y temperatures close toabsolute zero. In the study of classical electromagnetism it Vwasexpected and predicted that Y the resistance rof an .electricalconductor would decrease with a decrease in temperature.A The theoryindicated that an electric current through a conductor, Awhichconsists'ofthe flow'of'free `electrons through the crystal lattice ofthe moleculesv forming the conductor, would, be Vaffected by thethermal'vibrationof the 'atoms comprising the lattice structure. Thisseemed to indicate that at the 'higher temperatures the greater thermalactivity would absolute zero.

increasethe probability' of collisions'xbetween electrons, `and hence`result in vaV higher* resistivity. Conversely,` at theY lowertemperatures it was expected that the lower thermal activity of theelectrons would result in a lowering ofthe'resistance until some finitevalue was reached. This expected finite value yWa'sthough to consist ofcollisions between the'moving electrons forming the electriccurrentflowwith the substantially xed and immobile electrons forming thelattice structure. In addition, it was expected that defects and'impurities inthe lattice structure would also tend to establish a finiteresistance near At 4.2 degrees absolute, the electrical Y "resistanceofmercury is known ito vanish without even CAD the residual resistance aspredicted by the classical theory. For those materials exhibitngsu'perconductivity, the change between the normal conductive state andthe super- Y' conductive `,state is Yvery abrupt and occurs at aVspecific temperature' which is different for different materials. Thetemperature atfwhic'h the material changes-state is termed thetransition temperature `and is generally only a few `degreesabovefabsolute'zero; A"discus" sion of the principles ofsuperconductivity and a general listing of matevrialrsand r(,:ompou'ndsthat exhibit. the property of Vsuper- The above-listed transitiontemperatures apply only when Ythe materials are in asubstantiallyfzero'magneticeld.

Ineach'material the eldstrengthrequired to switch the state oftheconductor varies with temperaturevwithin the-range in which thematerialissperconductive. For example, the metal niobium hasY atransition temperature of 8 degrees' Kelvin at zerofield strength, acritical iield strength of 2000 oersterds a`t`4.2 degrees Kelvin, and acritical field strength of 2400'oer'steds at 1 degree Kelvin.

These lield'rstrengths', are determined to a, large degree by thepuritylof thematerialQthe mechanical stresses, and uponthe' generalorientation vof coiiguration of the'specimen being tested.. In certainconfigurations niobium has been Vfound -to'` have a criticaliieldstrength as high as 4000"oer`steds at'gapproxmatelygl degree` Kelvintemperature. vAt' thepre'senty time a popularV theory explaining thephenomenon of lsuperconductivit'y is that a fraction of thetotal-'population rof "currentr carrying electrons is /irst empty cell.

B2 line superconductive.

.3 paired in the sense that the resistance set up by the collision ofone electron is precisely offset by the rebound of its partner from asimultaneous collision, so that no net resistance to the current is setup. At temperatures above the transition point or in magnetic fields ofgreater than critical strength these electrons become unpaired and theircollisions are no longer self-canceling, but additive, and henceelectrical resistance is restored.

The crossed film gate utilizing this phenomenon is constructed of a gateelement crossed by one or more control elements that are separated fromeach other and from the gate element. The control elements may beconstructed of lead wires separated from each other so that the magneticfield of each separately controls the switching of the gate element. Inoperation, the complete device is immersed in a cryostat for maintaininga temperature that is lower than the critical transition temperature ofthe gate element. The cryostat may consist of a suitable container forholding the cryogenic materials in a liquid helium bath. A more detailedcryostat utilizing a double walled container in which the innercontainer holds the element in contact With the cryogenic materials andthe outer walls hold :a source of liquid nitrogen is fully described ina U.S. Patent 2,832,897 issued on April 29, 1958, to Dudley A. Buck. Forthe embodiment described, the gate element may be constructed of tin,which has a critical temperature of 3.7 degrees Kelvin. The controlelements may be constructed of lead having a critical temperature ofapproximately 7.2 degrees Kelvin, which is substantially higher than thetemperature of the cryostat. The uniqueness of the cryogenic device isthe apparent infinite ratio existing between the resistive state and thesuperconductive state. This high ratio permits many inputs with noattenuation of signals.

In future discussions concerning the switching of a cryogenic device itwill be assumed that the gate element is switched from a superconductivestate to a resistive state upon the passing of current in the associatedcontrol element. The control current will always be assumed to be ofsuiiicient value for effecting the desired switching action in the gateelement. Those situations requiring a different value of control currentwill be specifically pointed out and described.

Referring now to FIG. 2, there is shown a simplified schematic diagramillustrating how the control signals from the M register seek out andidentify the first empty cell preparatory to the writing of information.The first empty memory cell is identified as that available memory cellclosest to the M register. For purposes of illustra tion, three controlmodules representing three individual memory cells A1, A2, and An, areshown. The selection of the rst empty cell will be explained by assumingmemory cell A1 is full and that memory cells A2 and An are empty, whichthereby identifies memory cell A2 as the Associated with each controlmodule of each memory cell are busy circuits it?, 11, and 12, eacharranged to generate a signal on the E line if the individual memorycell is empty and hence available, or on the B line if the memory cellis full and hence unavailable. According to the original assumption,busy circuit It) will generate a signal on the B1 line thereby switchingdevice 13 into the resistive state as indicated by the crosshatchedlines, and leave device 14 which is in the 1 line superconductive. Thebusy circuit 11 Will generate a signal on the 1 32 line, since it isavailable, and hence switch device 15 into a resistive state, leavingdevice 16 which is in the It will be observed that every busy circuitwill generate a signall either on the B or line depending on theavailability of the memory cell.

Similarly, busy circuit i2 will generate a signal on the n line, therebyswitching device 17 resistive and leaving device 18 superconductive.

The current from source 19 is fed to all memory cells and is selectivelydirected by the individual outputs of each busy circuit. With thedevices set up as indicated, current from the source 19 will prefer thepath comprising the superconductive gate of device le, the controlelement of device 2t?, the superconductive gate of device 16, thecontrol element of device 20a and the control element of device 21 ofthe nth cell, after which the current is returned to the current sourcei9 to complete the direct current path. Consideration of the currentpath just traversed will show that the gate element of devices 2t?, i8,and Z1 will switch into a resistive state. In memory cell A1 a currentsource 22 feeds an output line labeled Select which consists of device20, and an output line labeled Non-Select which consists of device 23.Since device 2t) is resistive and device 23 is superconducting, anoutput signal will appear on the Non- Select line indicating that memorycell A1 is not available. A similar analysis for memory cell A2 willshow that a path is available from a current source 24 and out theoutput line labeled Select thereby indicating that cell A2 is the firstavailable memory cell. Cell An, which is representative of all emptycells after the first available cell will generate a current signal onthe Non-Select output line thereby indicating that the An-th memory cellis not the first empty cell. It can be seen, therefore, that only onememory cell will be chosen as the first available memory cell ready toreceive information.

Referring now to FIG. 3, there is shown a schematic diagram illustratinga control module and its functional cooperation with the M register andassociated memory module. The input lines identified as I, W1, W1, lVg,C1, and W3 all originate in the control module of the M register andsequentially connect all control modules of every memory cell.

The I line supplies a direct current from a suitable current sourcelocated in the M register. Current from the I line may pass eitherthrough devices 44 and 45 and out the V line into the memory module orthrough devices de and 47 and out the V line and into the memory module.As will be explained in connection with FIG. 4, the memory modulewriting operation is controlled by current appearing on the V line andis not affected by current appearing on the V line. The V and V outputlines from the memory module are joined together as indicated byreference 48 and are connected together to form the current source forthe R and lines of the same memory module. Current on the R lineindicates a matched or selected memory cell, whereas current in the Eline indicates a nonselected memory cell. Current on the R line wouldpass through devices 49 and 50 to a junction identied as point M.Current on the line would flow through devices 51 and 52 to point M. Itwill be recognized that regardless of the current path selected thetotal direct current will appear at point M. From point M to thejunction identified as point K on output line I, the current again has achoice of two paths which together form a busy flip-flop. By definitionwe have assumed that current flowing in a first path from point M topoint K comprising devices 54 and 55 will represent the ON conditionwhich indicates that the memory cell is not available for the storing ofnew information. A second path from point M to K of the busy flip-Hopcomprises devices 49, 56, and 57 and represents the OFF conditionindicating that the memory cell is available for the storing of newinformation. At point K the direct current is again combined and isdirected to the next control module of the next memory cell in the samemanner as described for the present control module.

A description of the various operations performed by the control moduleof each memory cell will now be given. It will be assumed that thepresent memory cell is available for the storage of information and thatit is the dened first memory cell. To satisfy this assumption, the busyflip-flop must be OFF thereby causing current to flow from M throughdevice 49, device 56, and device 57 to point K. In this state the gateelements of devices 49 and 57 will be switched resistive. Consideringnow'a writing operation, it is necessary for the M register to` generatea Write command signal on line W1. Since device 57 is resistive thewrite command signal will bey diverted through ldevices 44 Vand 55andback into lthe W1 line., The W1 lin'e is actually a return line forthe current signal appearing on the W1 line. The current pulse on lineW1 will therefore switch device 44 into aV resistiveV state and' causethe direct current from line I to` select the alternate path consisting'of (devices 46 and 47 Vandthe V line.` This direct current willswi'tchdevice 46 resistivey and supply thene'ces'sary control ini-theassociated memory module for causing a writingv operation The directcurrent will pass through'the memoryv module andvreappear at' point 48Awhere it becomeslrthe current' source for either Vthe R` `to ow to 'the'linewhich indicates that a true comparison has not beerivrna'de; YPriorto the .rea'din'gflop'eratiom it'is necessary to generate a reset signalon: the' Wsfli'ne to insure that thedirectl current in all memorymodules willl be'..directl'y 'initially to" the R line. Since only. one

memory cell `can be chosen, aA resistanceAV 'will' be placed in the Rline ofevery memory' module except the Vone containing thexdesiredrecord." The' -selected'memory rno'dule' will therefore vpass'l currenton the R line-through or line Vfor Athe samel memory module. v The exact`f path followed by the direct current will become apparent after "thesignals developed on lines W2 and W3V are ex plained. y In time sequenceand subsequent `to` the current puls'e'appearing on line -W1, a currentpulse termed a busy; control signal is generated inkth'e MV registerand` transmitted on line W2 in order to turn the` busy flip-flop of the"selected memory ycell into an ON condition to indicate that the memorycell is not available for the storage of information; Since device 46'-is resistive', the

current pulse 'on line W2fwi1l flow through device 45 and device 56thereby switching device V5'6v resistive. As mentioned previously,device 56'is in the OFF path of the busy flip-flop and has the effect oflswitching'the ilip- 'op so that current appearing at point M Will nowilowl through'device's 54 and 55 therebyswitching device 55 f resistive.A subsequent writecommand signal generated on line W1V will iind device-55fr'esistive and device 57 superconductive and will therefore passunaiec'ted to the next control module.` In `timesequence"an'd'subsequent to the pulse' appearing online W2, a currentpulse, termed aReset Signal, is generated in the M register and trans-Ymitted on vlinel W3 4to all control modules. The'Reset Signal 'willsvvitch'devicesf`4'7 and Y511 resistive., Thev switching' of device 47Aresistive prevents the dir'ectl'cu'rr'ent on line I from owing out theVline, and consequently medirsev 'current is' forced to new' out thev'line tiir'sugh devices 44 and-45Y causing device '45 to'becomeresistive. A subsequentbusy controlsignal generated on vline W2VwillV henceforth find device V45. resistive and'. device '46superconductive and willtherefore 'passthrough the conltrol module andonto the next control module. 'The 'reset'signal on lineW?I also switchesdevice 51` resistive which thereby prevents current flowing in eitherthe V or line; Device 51 therefore insures thatfthefcurrent lwill flowthroughtheR line `and through' devices49 and 50 to`fpoint M,whic'h, lofcourseywill switch device 50 devices 49 and' 5:0'to` point M; and frompoint M to point K' through the ON pathconsisting of: devices`54 'and5'5. Current on the R line will cause a 'nondestruc-t read-out Yof the'information contained in the memory rmodule of the; selectedrnemory cellintoi-the memory modul'eofr-the V M register'. TheY purpose of devices-49 andV 50- will be .explained in connection Withftheizclearingoperation:

The technique Jfor Yclearing a memory cell is simply to identifythe-information contained intheV memory cell and to `then turn* 'olf'the busy flip-ilop associated with that memory cell'to `thereby indicatethat the` memory celll is againavailablerfor the storing of information.In clearing a record, keyr 'information' is transmitted from the Y:memory module of 1 Mk-registervgto l all' memory modules ofV the memoryblock ,in-asimilar manner -as 'described in connectionY Withthe readingoperation. rIn lthe selected memory module'- current will appear Y, onthe R line and pass-through devices 49 and v50 thereby makingdevice 50'resistive. 'f A clearcommand signal is generated in the M register anddirected" online YC1 -t o all control modules. .In those selectedcontrol modules r'eceivingacurrenton .line R device Si'wwillfbeVresistive therebycausing the 'clear command signal to fl'owfthroughdevicesl 54 and 5 2out 'I effect-of this wouldbe to produce a currfvzntlonlibe-R line vof i anempty, ellhowevsf, )by @keine devis@ :49"i`ri1heOFF path ofthe busy nip-nop; the current owingon the R'line willrbeimpeded and caused-to flow ,onr the line Y inthe same manner as ifv afalse `comparison had occurred.

resistive. The current 'path frompoint M to Kv will-be the ON "pathofthe busy 'nip-flop consistingpof devices 5'4 andSS. TheV currentVpaths -just traversedindicate how.

a Write command signal' is'generated and directed into the VVline andalso4 how'the busy nip-flop is turned" ON to indicate to 'subsequentinterrogating pulses-that this particular memory cell is now noV4 longerAavailable Vforthe storing'o'f information. Y v, r

. Consider nowar'eading'o'peration in Whichkey information inthefmemorymodule' of tlieM register isrcom-V Yrnunicated toall memorymodules-.for the fpurp'ose Vof identifyi'ngra particular-stored record."The comparingjof transmitted key information ``and stored-key.information .will'be disclosed in connection with the-'descriptionacc-ompanying FIG; 4. However, at this point it is -necessary tounderstand lthat a true comparison in thememory moduler Will producea'superconductive -path' in 'theR'line whereas a false comparism4producesL a Vresistance *in* the R line which causes the:r current toflow 'in 'the lin'e.

Consequently, all memory modules except-the desired one'which containsthe storedl record will generate a resistancey in the Riline therebyrcausing the direct current ,ItVwill-be pointed out inmore detail-laterIthat-a nonunique Ykey mayv befusedin` clearing if it yshould be desira--ble to clearja rcomplete classV of records stored in a plu-.rality-of'rnemory cellsfg This-wouldsimply mean that in all of thoseselected memorycells current wouldappear .YonlineR.1.,-

Referring novi/gto vIiiAIC'it-t,there is 'illustrated' anlindividualgbit' handlingsegrnent of the kind that makes up thememorymodule. vEach rmemory'.module of every memory cellris composed of apluralitylof identical bit ,hand-ling, segments .illustratedin FIG! 4.,Asmentioned V,in connection with BIG. 43, theyV and lines originate inthe control'module andgar'e connected to .ther highest order, bithandling segment inthe memory module. The

. andVglines are connected sequentially toeach bit handling segmentcomprising thememory'module and then connected together to formthe-input current` source for line. Read farines..V The `vertical linesL and jo originate in the memory module of the Mregister anderer[sec'i'ue'n- -tially connected toV similar individual bit'v handlingsegments of'eachm'emory module comprisingthefmemory block. AThe'information signalis fed on line L during the 'w'riting' operation.' Thedirection yof' thecurrentpulse" represents'th'e informationin'the binaryform; for example,

it can be assumedthat currentmovingYV up line 4L willrepy resenta'binary 1 and current movirg'jdwn line L will represent a binary 0. The-L line serves'a dualpurpose ypaths which make up the persistor.

insufficient to switch device 59 resistive.

9 in that key information uniquely identifying the record may also betransmitted on line L when that particular bit handling segment is usedfor keying. It will be pointed out later how the mere selection of lineL for the transmitting of key information will determine the use of thesegment. Nonselection of any line L automatically causes that segment toread-out stored information on line O during the read operation. The Oline is used in connection with the nondestruct read-out of informationwhen the particular bit handling segment is used as a data storagesegment. The bit handling segment is best understood by assuming asituation in which a bit of information is to be Written. As explainedin connection with FIG. 3, the control module will direct the writecommand signal on line W1 into the V line of the selected memory cell.The V line in turn is connected to all bit handling segments comprisingthe memory module. A current on line V passes through the controlelement of device 5S thereby switching said device into a resistivestate. lt will be remembered that line V is sequentially connected toevery bit segment in the memory module and will therefore switch everyassociated device into a resistive state. In considering how theinformational current signal on line L is stored in the selected memorymodule, it is best to first consider the basic properties making up apersistor circuit. The explanation will be more readily understandableif we consider that the portion of line L in parallel with the gateelement of device 58 and control element of device 5'9 contains moreinductance than the parallel gate element path. The choice ofrinductances is governed primarily by optimum speed requirements of thedisclosed system. Where speed is not effective the choice of inductancemay differ as required by other parameters of the system. Theinformation current signal on line L will initially prefer the parallelpath of devices 58, 59 and control element dita of device di) since itis of lower inductance than line L. The gate element of device 53 havingbeen switched into a resistive state by a signal on line V willintroduce an IR drop which will cause the current to transfer to line L.Eventually, therefore, the complete information current will iiowthrough the higher inductance path in line L and completely bypass theparallel gate element of device 58. It must be remembered that in allother memory cells the gate corresponding to device S8 will besuperconducting,

' and hence the current path will consist of the low inductance path ofthe gate circuit and not the higher inductance path on line L. Theinformational current is stored by rst removing the write command signalon line V and then removing the information current signal on line L.When the current in line L is removed, a voltage develops across thenodes of the persister which causes a redistribution of the current inthe two parallel The current in the highly inductive path will tend toremain constant. The current in the other path will change in such a wayas to cause a total current of zero in line L. The result will be apersisting circulating current in the persistor loop. Its direction willbe counterclockwise to represent a binary l and clockwise to represent abinary 0, as deterymined by the direction of the original informationcur- `rent in line L. The absolute value of the information current online L is chosen to produce a circulating current in the persistor ofapproximately two-thirds the critical control current value necessary toswitch the gate element of device S9 from a superconductive to aresistive state. The circulating current by itself will therefore be If,for example, we assume an infinite ratio between the high inductancepath on line L and the low inductance path around the loop, then thevalue of the circulating current within the persistor loop will be thesame as the value of information current delivered on line L.

All individual bit handling segments store information comprising therecord. In addition there are two possible modes of operation for eachsegment. In one mode the CTI segment acts as a key element and comparesthe stored bit of information with the transmitted bit of information onthe L line. These comparisons result in the selection of the desiredrecord for reading or clearing. In the second mode the bit segment actsas a data element capable of transmitting a stored bit of information tothe M register in response to a true selection in the key bits. Thefirst' description given will explain the operation of the bit handlingsegment as a key element in which information is transmitted on line Lfrom the M register and is compared with information stored in theindividual segment. When used as a key element information istransmitted from the M register along line L in a manner similar to thatused in writing a record. The same conventions originally adhered to areused, that is, current going up for a binary l and down for a binary 0.Most of ythis informational current will take the path having the lowerinductance which has been defined as the parallel persistor loop path.lf the transmitted bit has the same value as the stored bit in a givensegment, the two currents will cancel in the persister loop path of thecircuit. However, should the two currents have different binary values,they will add. Since each current equals two-thirds the critical value,the sum of the two currents will exceed the critical value of device 59as originally set forth, device 59 will switch into a resistive state.The effect of this current on device 60 is of no consequence sincedevice 6@ is used only in the read operation. By way of review,therefore, it can be stated that if the transmitted key information isthe same as the stored information, there will be no effect on device59. However, should the transmitted information be different than thestored information, device 59 will become resistive. The producing of asingle resistive gate in the R line of any memory module willimmediately cause the current to select the line thereby indicating thatthat memory module is not being selected. In effect only a truecomparison in all key elements will produce a completely superconductiveR line. Gate 59 of each individual bit handling segment not used as akey element will remain superconductive and thereby not effect theresistance of the R line.

As mentioned above, the second use of the individual bit handlingsegment is as a data element. By assuming that the required keyinformation was transmitted from the M register in the appropriatenumber of individual bit handling segments to uniquely identify a storedrecord, we can assume that current will iiow in the R line of theselected memory module. lf the current flowing in line R through gate@db of device o@ is in the same direction as the circulating currentiiowing through the gate 69a, then device 6i? will be switchedresistive. In the alternative, if the direction of the current in line Ris opposite to the circulating current, then device 6@ will remainsuperconductive. The only condition that can cause the sum of controlcurrents in device 60 to exceed the critical value is for current toexist in the R line and to have the same direction as the circulatingcurrent. By a proper choice of the direction of the current in the Rline, device dit will become resistive if, and only if, that particularmemory cell is selected and that particular individual bit handlingsegment contains a binary l. The resulting resistance orsuperconductivity existing in line O is detected by read amplifiers inthe memory module of the M register. These amplifiers are connected toeach line O for each individual bit handling segment. For example, abinary l is detected by the presence of a voltage across a singleresistive O line, whereas a binary 0 is detected by the absence of avoltage developed across the superconductive line.

Referring now to FlG. 5, there is shown a cross section of a dualcontrol device having two control elements, such as device 6thillustrated in FIG. 3. The device is usually built on a suitablesubstrate material that is covered by a thin film of insulatingmaterial. The gate element is bonded to the insulating material, and asecond zero,a binary 1, andy a binary 1 respectively.

insulating film coversthe gate' element. yThe first control l `elementis bonded on the insulator film and may be placed longitudinally ortransversely with .respect to the gate element. The first controlelement is covered by a third layer of a thin insulating film andthesecond control gate is bonded to said third layerfof insulatingmaterial. Both the first and s'econdcontrol elements are placed in thesame plane and are madeV as identical to eachother as lpossible.. Whenthe currents in both control elements are in thesame direction, themagnetic fields add and there-- by switch the .gate element from asuperconductive state to la resistive state. 'The' current levels ineither of control Aelements 1 or 2 may be chosen so that either controlelement canswitch the gate element, or, as in the example vjustdescribed, the magnetic fields 'of both elements must combi/ne toswitchthe gate element.` .The geometry of theltwo control elements. is suchthat the associated gate element will be switched resistive if vthecontrol currents in the control elements are inthe same direction, and,conversely, the gate element willremain superconductive if'thecontrolcurrents are in opposite directions.

Referring now to FIG. 6 there is illustrated a complete memory blockcomprising three memory cells, identified as' cell-1, cell 2, and cell3. Forrthe purposevof illustrating the operation of the disclosed memoryblock we' will'.

assume that cell 1 and cell n are full of information, and hence thebusy nip-flop in each control module` will be ON. We will assume furtherthat cell 2 is available for lthe storage of information, and hence thebusy flip-flop Willbe OFF.V The record handling capabilities of thislsystemfare'l'irnited to four independent bit handling segmentsidentified asrbit segments 1, 2, 3, and 4'. The information stored intheindividual bitrsegments 1, 2, 3,-

-an'd 4 comprising the memoryY module of cell 1 will be assumed to be abinary 1, a binary l, a binary zero, and a binary zero respectively. Theinformation storedinthe 'segments 1,- 2, 3, and 4 comprising the memorymodule of cell n will be assumed' to be a binary zero, a binary Y Inlkeeping with the original assumptions set forth ear- Vlier'in describingthe individual memory'modules it will berrecalled that a binary l isrepresented by va circulating counterclo'ckwise current within'thepersist-or circuit defined fbyrdevice 58 located in the individualmemory modules. The binary is, of course, represented by a Y Vclockwisecirculating current within the persistor circuit. The operationl of Ythesystem will now befdescribed by illustra-tinga writing Voperation inwhich the individual bit handlingsegments 1, 2, 3, and 4 comprising thememory module of the MV register will transmit a binary 0, a binary Ydevices 47 `and 51 on line'W3 to be switched resistive. At

vSand 55 aridout the W2 line to cell n. l, the busy control signalbeingbypassed is to switch device the termination of the 'reset pulse,I theassociateddevices return to their superconductive state. Subsequentoperationswill not change the flow of the direct current from 4the Vliney into theyVY line' even though both lines are w superconductive,unless, of course, an impedance in the form of a resistive deviceis-placed in either of the lines. As `a result,the directV currentin allmemory cells will flow out Athe line Withthe exception )of cell 2inwhich the 'current will'be switchedinto the V line by the action of"device 44 being switched resistive. f

After 'the information is writteninto memory cell 2 a busy controlsignal on line W2 is transmitted. This signal will pass through'deviceY46 of cell 1 since device 45 is vvresistive and'device 46 issup'erco'nductive.V However, in

cell 2 device/t6 is resistive and device 4S superconductive, therebycausing the signal to be bypassed through ydevice The effect of S6resistive thereby resettingthe busyflip-flop-in cell 2.

jAs mentioned previously, a resetsignal is transmitted on line W3 tore-establish the DC. Lcurrent in lines 'V and R preparatory to the nextoperation.

in' table form the information .stored in the individual bit handlingsegments comprising the individual memory Vmodulesfor each memory cellis as follows:

n able l Bit Handling Segments Memory Cell l No. 1 VNo. 2i NQ, 3 No. 4

In orderv'toV 'readvinformation stored in any of cells 1, 2 or 3, itisnecessary to select those bit handlin'gsegments that uniquely identifythe stored information Wanted.` A

review of Table I will show the information contained Y in c ell 3' maybe uniquelyl identified in a number'of Ways,

1, a binary l, and a binary 0 respectively into the memory 'modules forstorage. In time-sequence a write command vsignal isapplied on line'Wlof the M register. vThis signal willy pass through device ,S7 of cell. 1whichis superi conductive and continue to'cell l2. In cell 2 the busyflip-f. op is off, and hence device 5.7 is resistive, causing the iwrite Vcom'ir'iand vsignal to passthrough device 44 and device v to theW1 line. This action willrcause device 44: of jcell Z to switchresistive and direct the current on .line I feeding'cell 2 topassthrough device 46 and47 and out the Y` line'. I

Sincethe V line is connected to all control elements of ldevice 58 itwill be apparent'that each device 58m every bit' handling segment' incell 2 will be switched resistive.

As mentioned previously, informational current from the vrrfeinory'module of the M register is transmitted on y'each Wline'in Vaccordancewith the convention that a binary vl current 'is directed up the L llineanda binary zero' current vdown the L line. This" information current online L will 4not be affected by either of cell 1 or cell3 but on'ly'by`tion 'of information key current online L in .both segments lfor-example,fby segments l'and 2, 2 and 3, 3- and'4, 1 and 4, Vand 2 and4,'just to mentionV only combinations of two. A similar analysis can bemade for theinformatio'n contained in' cell 2 and 'cell'y 1f. y. Inorder-to illustrate the readingoperation we willfassume the informationcontained in cell 3 isdesir'e'dand that our key uniquely identifyingthe'storedv record is the information that bithankdling segmentslfand 2 eachcontain a binary O. Prior 'toreadinga reset signal is generated andtransmitted on line to insure that direct current will ow on all 'Vlines and' on all R lin'es in every memory cell. The selec- 1 and 2will'have the effect of switching at least one de- Yvice'59v resistivein every memory cell butthe selected cell 2, slince'vcurrnt in theV'lineof cell 2 has caused"v each device 58 to bev resistive,thereby directingthe cur- Yrent Within the' persistor circuit as'previously-describedl inconnection with, FIG. j4..

' Byway ofireview, the Ibusy nip-flop in cell 1 is ON.

one. The result is thatgonlyv'o'ne line R will vremain superconductiveafter the informationkey current is transmitted and that the memory cellcontaining the super- "conductiv'e line' Rwill contain the desired.information.

1n all nonselected memory cellsA line' R will become resistivel therebycausing the'V current to flow through line In those memory cellscontainingl a binary 1, vthe .circulating current,andfthe informationalcurrent will add causing device 59 to become resistive.- An'analysis ofthe conditions now existing in cell n will show that device conductive;

59`in segment 1 and device 59 in segment 2 are super- In cell 2 it canbe shown that device S9 in segment l is superconductive, whereas device59 in segment 2 is resistive. In cell 1 device 59 in segment 1 anddevice 59 in segment 2 will both be resistive. With respect to segments3 and d in which no information current was transmitted on line L, thedevice 5f in both segments 3 and 4 will remain superconductive.

As mentioned previously the direction of current on line R is chosen sothat circulating current representing a binary l in the persistorcircuit of the individual segment combines with the current in the Rline to switch the dual control device 6ft. This, of course, will occuronly in segments 3 and 4 of cell n. The state of resistance of gate di)in segments 3 and 4 is determined by read amplifiers in every line O inthe M register. The read amplifiers connected to the O lines of segments3 and 4 will detect a resistance on line O, thereby indicating a binaryl was stored in segments 3 and 4 of cell 3.

The clearing operation is best explained by assuming that a class ofcells identified as those having a binary 0 in segment l and a binary lin segment 3 are to be cleared in the memory block. A review of Table Iwill show that such a class consists of cells 2 and n. The operation ofclearing is very similar to that of reading in that current representinga binary 0 is transmitted on line L of segment 1 and currentrepresenting a binary l is transmitted on line L of segment 3. Cells 2and n Will compare thereby making line R superconducting in both cellswhereas in cell 1 line R will become resistive. Simultaneously, a clearcommand signal is transmitted from the M register on line C1 and willpass through device Si) of cell l. and be bypassed in cell 2 throughdevice 54 and device 52, and similarly in cell n will be bypassedthrough devices 54 and 52.

As previously described, this action will reset the busy flip-fiopcircuit from the ON condition to the OFF condition for both cells 2 andn, thereby indicating to future write command signals appearing on lineW1 that cells 2 and nare now available for storage of information. T heillustration of clearing just given very graphically shows how more thanone record may be cleared at one time by utilizing non-unique keyinformation.

This completes the descriptions of the embodiments of the inventiondisclosed and illustrated here. However, many modifications andadvantages will be apparent to persons skilled in the art withoutdeparting from the spirit and scope of this invention. A review of thepresent invention as compared to the previously referred to copendinginvention will indicate that the functions of key and data have now beenconsolidated into a single unit which can serve in either role,depending only upon the signals impressed upon the L line in the Mregister. In fact, any bit handling segment in any of the memory cellscan serve in different roles from one read operation to the next. TheL/R time constant of the present invention is improved by a factor equalto the number of bits used in the key portion of the referencedapplication, since in the present invention a word of record is selectedfor reading or clearing by the absence of resistance in the R line.Therefore, it is only necessary to detect the resistance of one of anumber of gates connected in series. In the previously referencedapplication the comparing line was connected to a number of gates inparallel, thereby making it necessary to detect the resistance of aparallel combination in which all resistive gates are in parallel.Accordingly, it is desired that this invention not be limited to theparticular details of the embodiments disclosed except as defined by theappended claims.

The embodiments of the invention in which an exclusive property orprivilege is claimed are defined as follows:

i. A superconductive memory system comprising a plurality ofsuperconductive memory cells, a plurality of circulating currentpersistor circuits in each memory cell for storing bits of informationcomprising a complete record, transmitting means interconnectingcorresponding lliindividual persistor circuits of each memory cellwhereby bit information is simultaneously transmitted to each memorycell, said transmitting means adapted to transmit key bits ofinformation on selected bit positions only, said key bits of informationuniquely identifying only a single complete stored record, asuperconductive comparing means located in each bit position of everymemory cell for comparing said stored bit of information with said keybit of information, each memory cell comprising a superconductiveselecting means responsive to a true comparison in all key bit positionsas indicated by a series superconductive line in all key bit positions,and superconductive means in each memory cell responsive to a truecomparison as indicated by said selecting means for indicating thestored bits of information.

2. A superconductive memory system comprising a plurality ofsuperconductive memory cells, a plurality of circulating currentpersistor circuits in each memory cell for storing bits of informationComprising a complete record, said persistor circuit storing a bit inthe binary form whereby current circulating in one direction representsa binary l and current circulating in the opposite direction representsa binary 0, transmitting means interconnecting corresponding individualpersistor circuits of each memory cell whereby bit informa-tion issimultaneously transmitted to each memory cell, said transmitting meansadapted to transmit key bits of information on selected bit positionsonly, said key bits of information uniquely identifying only a singlecomplete stored record, .a superconductive comparing means located ineach bit position of every memory cell for simultaneously comparing saidstored bit of information with said key bit of information, each memorycell comprising a superconductive selecting means responsive to a truecomparison in all key bit positions as indicated by a seriessuperconductive line in all key bit positions, and superconductive meansin each memory cell responsive to a true comparison as indicated by saidselecting means for indicating the stored bits of information.

3. A superconductive memory system comprising a plurality ofsuperconductive memory cells, a plurality 4of circulating currentpersistor circuits in each memory cell for storing bits of informationcomprising a complete record, said persistor circuit storing a bit inthe binary form whereby current circulating in one direction representsa binary l and current circulating in the opposite direction representsa binary O, transmitting means interconnecting corresponding individualpersistor circuits of each memory cell whereby bit information issimultaneously transmitted in the binary form to each memory cell, saidbit information being transmitted as a current signal whereby current inone direction represents a binary 1 and current in the oppositedirection represents a binary 0, said transmitting means adapted totransmit key bits of information on selected bit positions only, saidkey bits of information uniquely identifying only a single completestored record, a superconductive comparing means located in each bitposition of every memory cell for comparing said stored bit ofinformation with said key bit of information by algebraically combiningsaid transmitted key current with said stored circulating persistorcurrent, each persistor circuit comprising a superconductive deviceresponsive to said algebraically combined key current and persistorcurrent for controlling the state of said device, all of said devices ineach memory cell being connected in series, each memory cell comprisinga superconductive selecting means responsive to a true comparison asindicated by all of said series devices being superconductive, andsuperconductive means in each memory cell responsive to said selectingmeans for indicating the stored bits of information.

4. A superconductive memory system comprising a plurality ofsuperconductive memory cells, a plurality of circulating currentpersistor circuits in each memory cell for storing bits of informationcomprising a complete record, said A.persister'circuit storing a bit in-the, binary form -Whereby cur-rent"circulating in one directionrepresents va -binar-y 1 and current circulating in the `opposite cell,said bit information beingtransmitted asa current signal wherebycur-rent in one direction `representsva binary H1 -and current in Vfthe-oppositedirection represents a binary 0, Asaid transmitting meansadapted to transmit key bits lof yinformation-on selected 'bit4positionsyonly, said key bits of information uniquely identifying onlya sin'gle complete-stored record, -a superconductive comparing meanslocated in'e'achbit position of every memory` cel1'for'comparing saidstored bit Vof information with said zkey'bit lof informationbyalgebraica11y combining ,'said transmitted key currentwth saidstored-lcirculating persister currentfeaeh persister circuit comprising`a -superconductive-device responsive 'to said algebraically combinedfkeycurrent and persister current -for controlling the state-ofsaid-device, al1 of saiddevices in each memory cellfbeing'connected -inseries, 'each memory cell comfatrue comparison as indicated` byfall ofsaid series devices Y being superc-onductive, superconductive means in`each Y -Referencescited Bythel'zxminer" lUNITED Y'STATES PATENTS 'Y 110 2,736,880542/5613Forresfe v r 340-174 2,775,725?? I2/ 5651 SinkS40-+347 21933359* 5/,61 fGr'ejen-; c 3210-417311 v3,021,451011Y l27/62' Anderson t 340-1731 j 3,"031'5650 4/62 Koemerl3401-174 153,048,182?, `/8/62-Wrigh't-v 340-174 #3,108,255 1o/63 itichholz 340-17253,108,257- 10/63 Buchhlz S40-172.5

,90, 'OTHERREFERENCES' vnait/1 Technialni'sdosure Ballena, Rosin,Assciaave Memor-y; v01; 3, No. 11i-March 1961, pp; 1z0-22.

ravfrN'G L. SRAGOW, PrimaryV Examiner.

1. A SUPERCONDUCTIVE MEMORY SYSTEM COMPRISING A PLURALITY OFSUPERCONDUCTIVE MEMORY CELLS, A PLURALITY OF CIRCULATING CURRENTPERSISTOR CIRCUITS IN EACH MEMORY CELL FOR STORING BITS OF INFORMATIONCOMPRISING A COMPLETE RECORD, TRANSMITTING MEANS INTERCONNECTINGCORRESPONDING INDIVIDUAL PERSISTOR CIRCUITS OF EACH MEMORY CELL WHEREBYBIT INFORMATION IS SIMULTANEOUSLY TRANSMITTED TO EACH MEMORY CELL, SAIDTANSMITTING MEANS ADAPTED TO TRANSMIT KEY BITS OF INFORMATION ONSELECTED BIT POSITIONS ONLY, SAID KEY BITS OF INFORMATION UNIQUELYIDENTIFYING ONLY A SINGLE COMPLETE STORED RECORD, A SUPERCONDUCTIVECOMPARING MEANS LOCATED IN EACH BIT POSITION OF EVERY MEMORY CELL FORCOMPARING SAID STORED BIT OF INFORMATION WITH SAID KEY BIT OFINFORMATION, EACH MEMORY CELL COMPRISING A SUPERCONDUCTIVE SELECTINGMEANS RESPONSIVE TO A TRUE COM-